Need Junior/Senior engineers for IC design verification
Requirements: Preferred to be MSEE with 2 years, or BSEE with 3 years experience in digital ASIC/SOC design verification.

  1. Should have good understanding on ASIC/SOC design & verification flow
  2. Good knowledge of design verification methodology, such as UVM or OVM.
  3. Experiences with simulation model creation & test bench build
  4. Familiar with scripting language, such as Perl, C shell, Make file
  5. Cooperation with SoC or subsystem level engineers on verification work
  6. SMTS level candidate should be able to lead the DV architect work inside & cross team.
    It is a plus if the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, PCIe protocol.
    The successful candidate will apply current functional verification techniques to perform & improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. Senior candidate should be able to work independently on various DV tasks & providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for new design, block & chip level test plan creation & implementation, coverage analysis & regression cleanup.

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